A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation

Conference object, Preprint English OPEN
Lee, Jae-Gon; Chung, Moo-Kyoung; Ahn, Ki-Yong; Lee, Sang-Heon; Kyung, Chong-Min;
  • Publisher: HAL CCSD
  • Subject: [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] | [ INFO.INFO-AR ] Computer Science [cs]/Hardware Architecture [cs.AR] | Computer Science - Performance | [SPI.TRON]Engineering Sciences [physics]/Electronics | [ SPI.TRON ] Engineering Sciences [physics]/Electronics

Submitted on behalf of EDAA (http://www.edaa.com/); International audience; This paper presents a scheme for efficient channel usage between simulator and accelerator where the accelerator models some RTL sub-blocks in the accelerator-based hardware/software co-simulati... View more
  • References (12)
    12 references, page 1 of 2

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    [9] J.-G. Lee, W. Yang, Y.-S. Kwon, Y.-I. Kim, and C.-M. Kyung. Simulation Acceleration of Transaction-Level Models for SoC with RTL sub-blocks. In Proceedings of the Asia South Pacific Design Automation Conference, Jan. 2005.

    [10] W. Muller, W. Rosenstiel, and J. Ruf. SystemCTM: Methodology and Applications. Kluwer Academic Publishers, 2003.

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