Computationally efficient implementation of sarse-tap FIR adaptive filters with tap-position control on intel IA-32 processors

Conference object English OPEN
Hirano, Akihiro ; Nakayama, Kenji (2008)
  • Publisher: IEEE = Institute of Electrical and Electronics Engineers
  • Journal: The International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2008) 292-295

This paper presents an computationally ef cient implementation of sparse-tap FIR adaptive lters with tapposition control on Intel IA-32 processors with single-instruction multiple-data (SIMD) capability. In order to overcome randomorder memory access which prevents a ectorization, a blockbased processing and a re-ordering buffer are introduced. A dynamic register allocation and the use of memory-to-register operations help the maximization of the loop-unrolling level. Up to 66percent speedup is achieved.
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