Share  Bookmark

 Download from


[1] Semiconductor Industry Association, “International Technology Roadmap for Semiconductors,”, 2001.
[2] A. Svizhenko, M. P. Anantram, T. R. Govindan, B. Biegel, and R. Venugopal, “Two dimensional quantum mechanical modeling of nanotransistors,” J. Appl. Phys., vol. 91, pp. 23432354, 2002.
[3] Z. Ren, R. Venugopal, S. Datta, and M. Lundstrom, “Examination of design and manufacturing issues in a 10 nm double gate MOSFET using nonequilibrium Green's function simulations,” IEDM Tech. Dig., pp. 107110, 2001.
[4] B. Yu, H. Wang, A. Joshi, Q. Xiang, E. Ibok, and M.R. Lin, “15 nm gate length planar CMOS transistor,” IEDM Tech. Dig., pp. 937941, 2001.
[5] D. J. Frank and Y. Taur, “Design considerations for CMOS near the limits of scaling,” SolidState Electron., vol. 46, pp. 315320, 2002.
[6] D. Hisamoto, “FD/DGSOI MOSFET  A viable approach to overcoming the device scaling limit,” IEDM Tech. Dig., pp. 429532, 2001.
[7] A. Asenov, A. R. Brown, J. H. Davies, and S. Saini, “Hierarchical approach to 'atomistic' 3D MOSFET simulation,” IEEE Trans. ComputerAided Design, vol. 18, pp. 15581565, 1999.
[8] C. S. Rafferty, B. Biegel, Z. Yu, M. G. Ancona, J. Bude, and R. W. Dutton, “Multidimensional quantum effects simulation using a densitygradient model and scriptlevel programming technique,” in Proc. SISPAD, K. De Meyer and S. Biesemans, Eds., 1998, pp. 137140.
[9] S. Jallepalli, J. Bude, W.K. Shih, M. R. Pinto, C. M. Maziar, and A. F. Tasch Jr, “Electron and hole quantization and their impact on deep submicron silicon p and nMOSFET characteristics,” IEEE Trans. Electron Devices, vol. 44, pp. 297303, 1997.
[10] D. J. Frank, Y. Taur, and H.S. P. Wong, “Monte Carlo modeling of threshold variation due to dopant fluctuations,” in Proc. Symp. VLSI Technology, 1999, pp. 169170.