In this paper we study the amplitudes of random telegraph signals (RTS) associated with the trapping of a single electron in defect states at the Si/SiO/sub 2/ interface of sub-100-nm (decananometer) MOSFETs employing three-dimensional (3-D) "atomistic" simulations. Bot... View more
 S. Thompson, M. Alavi, R. Argavani, A. Brand, R. Bigwood, J. Brandenburg, B. Crew, V. Dubin, M. Hussein, P. Jacob, C. Kenyon, E. Lee, M. Mcintyre, Z. Ma, P. Moon, P. Nguyen, M. Prince, R. Schweinfurth, S. Shvakumar, P. Smith, M. Stettler, S. Tyagi, M. Wei, J. Xu, S. Yang, and M. Bohr, “An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7-1.4 V,” in IEDM Tech. Dig, 2001, pp. 257-260.
 R. Chau, J. Kavalieros, B. Roberds, S. Schenker, D. Lionberger, D. Barlage, B. Doyle, R. Arghavani, A. Murthy, and G. Dewey, “30 nm physical gate length transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays,” in IEDM Tech. Dig, 2000, pp. 45-48.
 S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokozono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, T. Matsushita, S. Magoshi, Y. Watanabe, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, “High performance 35 nm gate length CMOS with NO oxinitride gate dielectric and Ni SALACIDE,” in IEDM Tech. Dig, 2001, pp. 641-644.
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