This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high thro... View more
 E. Mirsky and A. DeHon, “MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources,” in Proc. IEEE Symposium on FPGAs for Custom Computing Machines, pp. 157-166, 1996.
 M. Cocco, J. Dielissen, M. Heijligers, A. Hekstra,J. Huisken, S. Hive, and N. Eindhoven, “A scalable architecture for LDPC decoding,” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition, vol.3,pp- 88-93, 2004.
 Mike Butts, "Synchronization through Communication in a Massively Parallel Processor Array," IEEE Micro, vol. 27, no. 5, pp. 32-40, September/October, 2007.
 Z. Yu, M. Meeuwsen, R. Apperson, O. Sattari, M. Lai, J. Webb, E. Work, D. Truong, T. Mohsenin, B. Baas, "AsAP: An Asynchronous Array of Simple Processors,"IEEE Journal of Solid-State Circuits (JSSC), vol. 43, no. 3, pp. 695-705, 2008.
 S. Purohit, S. Chalamalasetti, M. Margala, P. Corsonello,"Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices," in Proceedings of International Conference on Reconfigurable Computing and FPGAs, pp. 217-222, 2008.
 S. Krithivasan, M.J Schulte, "Multiplier architectures for media processing," Record of the 37th Asilomar Conference on Signals, Systems and Computers, pp. 2193-2197, 2003.
 M. Lanuzza, S. Perri, P. Corsonello, M. Margala, "A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications," 2nd NASA/ESA Conference on Adaptive Hardware and Systems, pp-119-126, 2007.
 A. Karandikar, K.K Parhi, "Low power SRAM design using hierarchical divided bit-line approach ," Proceedings of International Conference on Computer Design, pp. 82-88, 1998.
 M. Lanuzza, S. Perri, P. Corsonello,” MORA- A New Coarse Grain Reconfigurable Array for High Throughput Multimedia Processing”, Proceedings of International Symposium on Systems, Architecture, Modeling and Simulation,( SAMOS), pp-159-168, 2007.