MORA - an architecture and programming model for a resource efficient coarse grained reconfigurable processor

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Chalamalasetti, S.R.; Purohit, S.; Margala, M.; Vanderbauwhede, W.;
  • Publisher: IEEE Computer Society
  • Subject: QA75

This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high thro... View more
  • References (10)

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