On the nature and effect of power distribution noise in CMOS digital integrated circuits

0044 English OPEN
Johnstone, Kevin Kennedy;
  • Subject:
    acm: Hardware_INTEGRATEDCIRCUITS

The thesis reports on the development of a novel simulation method aimed at modelling power distribution noise generated in digital CMOS integrated circuits. The simulation method has resulted in new information concerning: 1. The magnitude and nature of the power distr... View more
  • References (12)
    12 references, page 1 of 2

    Introduction 1. Research Objectives.... '" ..................................... '" ............... '" .. 1 2. Scope of Thesis .......................................................................... 1 3. Thesis Structure ........................................................................2 4. Statement of Originality ............................................................3

    1.5 Power Distribution 1.5.1 Simultaneous Switching Noise ................................. 18 1.5.2 Noise Reduction .......................................................20

    1.6 Conclusions............... '" ..................................,......................22

    2. Power Distribution Noise Analyses 2.1 Introduction ..........................................................................23 2.2 The Delta-I Simultaneous Switching Problem .........................23 2.3 Ground Bounce Control in CMOS Integrated Circuits ........... 24 2.4 Power Bus Transients in Very High Speed Logic Systems .......25 2.5 Noise Generation Analysis and Noise-Suppression Design Techniques ................................................................27 2.6 A CMOS Mainframe Processor with 0.5um Channel Length ...30 2.7 Conclusions...........................................................................31

    3. Power Distribution Noise in an Array-based Architecture 3.1 Introduction ..........................................................................34 3.2 Architectural Overview 3.2.1 Systolic Architectures: the Basic Principle ................34 3.2.2 A Bit-level Systolic Array for MatrixVector Multiplication................................................36 3.2.3 A Systolic Array for Correlation ................................37 3.2.4 An "efficient" Systolic Array for Distance Computation............................................................39 3.2.5 Conclusions ....................................... '" ..................42 3.3 The Development of a Simulation Mode 3.3.1 Overview of Requirements ....................................... .42 3.3.2 Clock Distribution Modelling ....................................43 3.3.3 Current Flow Modelling ........................................... .44 3.3.4 Synthesising an Array ..............................................52 3.3.5 The Power Distribution Network ...............................54 3.3.6 Noise Predictions......................................................58 3.3.7 Non-standard Technology.........................................64

    3.4 Perfonnance Implications 3.4.1 Assessment Methodology..........................................65 3.4.2 Perfonnance Assessment .........................................66

    3.5 Noise Model Sensitivity 3.5.1 Assumption-related Issues .......................................69 3.5.2 Relative Sensitivity ...................................................70

    3.6 Conclusions 3.6.1 Simulation Model .....................................................72 3.6.2 Perfonnance Limitations .........................................73

    5. Transient Latch-up and Electromigration 5.1 Transient Latch-up 5.1.1 Introduction ........................................................... 129 5.1.2 Simulation Model and Methodology ........................ 129 1. Noise Modelling Methodology.............................. '" ...... 138 2. The Nature of the Noise ............................................... 139 3. A More Automated Approach ....................................... 140 4. Predicted Consequences .............................................. 140

    References ............................................................................ ...... '" ...... 142

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