publication . Article . 2014

Inverse scaling trends for charge-trapping-induced degradation of FinFETs performance

Amoroso, Salvatore Maria; Georgiev, Vihar P.; Gerrer, Louis; Towie, Ewan; Wang, Xingsheng; Riddet, Craig; Brown, Andrew Robert; Asenov, Asen;
Open Access English
  • Published: 01 Dec 2014
  • Publisher: IEEE
  • Country: United Kingdom
In this paper, we investigate the impact of a single discrete charge trapped at the top oxide interface on the performance of scaled nMOS FinFET transistors. The charge-trapping-induced gate voltage shift is simulated as a function of the device scaling and for several regimes of conduction-from subthreshold to ON-state. Contrary to what is expected for planar MOSFETs, we show that the trap impact decreases with scaling down the FinFET size and the applied gate voltage. By comparing drift-diffusion with nonequilibrium Green functions simulations, we show that quantum effects in the charge distribution and transport can reduce or amplify the impact of discrete tr...
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Modelling of the reliability and degradation of next generation nanoelectronic devices
  • Funder: European Commission (EC)
  • Project Code: 261868
  • Funding stream: FP7 | SP1 | NMP
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Salvatore Maria Amoroso (S'10-M'12) received the Ph.D. degree in electronics engineering from the Politecnico di Milano, Milan, Italy, in 2012. He has been an Associate Researcher with the Department of Electronics, University of Glasgow, Glasgow, U.K., since 2012.

Vihar P. Georgiev received the Ph.D. degree from the University of Oxford, Oxford, U.K., in 2011. He joined the Device Modelling Group with the School of Engineering, University of Glasgow, Glasgow, in 2011, where he is currently a Post-Doctoral Research Assistant.

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