Inverse scaling trends for charge-trapping-induced degradation of FinFETs performance

Article English OPEN
Amoroso, Salvatore Maria; Georgiev, Vihar P.; Gerrer, Louis; Towie, Ewan; Wang, Xingsheng; Riddet, Craig; Brown, Andrew Robert; Asenov, Asen;
(2014)

In this paper, we investigate the impact of a single discrete charge trapped at the top oxide interface on the performance of scaled nMOS FinFET transistors. The charge-trapping-induced gate voltage shift is simulated as a function of the device scaling and for several ... View more
  • References (14)
    14 references, page 1 of 2

    [1] D. A. Antoniadis and A. Khakifirooz, “MOSFET performance scaling: Limitations and future options,” in IEDM Tech. Dig., Dec. 2008, pp. 1-4.

    [2] D. Linten, G. Hellings, S.-H. Chen, and G. Groeseneken, “ESD in FinFET technologies: Past learning and emerging challenges,” in Proc. IRPS, Apr. 2013, pp. 2B.5.1-2B.5.8.

    [3] H. Kawasaki et al., “Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond,” in IEDM Tech. Dig., Dec. 2009, pp. 1-4.

    [4] M. Toledano-Luque et al., “Degradation of time dependent variability due to interface state generation,” in Proc. Symp. VLSI Technol., Jun. 2013, pp. T190-T191.

    [5] GARAND Version 2014.2. [Online]. Available: http://www.goldstandardsimulations.com

    [6] A. Martinez, M. Aldegunde, N. Seoane, A. R. Brown, J. R. Barker, and A. Asenov, “Quantum-transport study on the impact of channel length and cross sections on variability induced by random discrete dopants in narrow gate-all-around silicon nanowire transistors,” IEEE Trans. Electron Devices, vol. 58, no. 8, pp. 2209-2217, Aug. 2011.

    [7] K. Nehari, N. Cavassilas, J. L. Autran, M. Bescond, D. Munteanu, and M. Lannoo, “Influence of band structure on electron ballistic transport in silicon nanowire MOSFET's: An atomistic study,” Solid-State Electron., vol. 50, no. 4, pp. 716-721, Apr. 2006.

    [8] S. M. Amoroso, L. Gerrer, M. Nedjalkov, R. Hussin, C. Alexander, and A. Asenov, “Modeling carrier mobility in nano-MOSFETs in the presence of discrete trapped charges: Accuracy and issues,” IEEE Trans. Electron Devices, vol. 61, no. 5, pp. 1292-1298, May 2014.

    [9] X. Wang, A. R. Brown, B. Cheng, and A. Asenov, “Statistical variability and reliability in nanoscale FinFETs,” in Proc. IEDM, Dec. 2011, pp. 5.4.1-5.4.4.

    [10] B. Kaczer et al., “The relevance of deeply-scaled FET threshold voltage shifts for operation lifetimes,” in Proc. IRPS, Apr. 2012, pp. 5A.2.1-5A.2.6.

  • Metrics
Share - Bookmark