FinFET centric variability-aware compact model extraction and generation technology supporting DTCO

Article English OPEN
Wang, Xingsheng ; Cheng, Binjie ; Reid, David ; Pender, Andrew ; Asenov, Plamen ; Millar, Campbell ; Asenov, Asen (2015)
  • Publisher: Institute of Electrical and Electronics Engineers
  • Related identifiers: doi: 10.1109/TED.2015.2463073
  • Subject:

In this paper, we present a FinFET-focused variability-aware compact model (CM) extraction and generation technology supporting design-technology co-optimization. The 14-nm CMOS technology generation silicon on insulator FinFETs are used as testbed transistors to illustrate our approach. The TCAD simulations include a long-range process-induced variability using a design of experiment approach and short-range purely statistical variability (mismatch). The CM extraction supports a hierarchical CM approach, including nominal CM extraction, response surface CM extraction, and statistical CM extraction. The accurate CM generation technology captures the often non-Gaussian distributions of the key transistor figures of merit and their correlations preserving also the correlations between process and statistical variability. The use of the hierarchical CM is illustrated in the simulation of FinFET-based SRAM cells and ring oscillators.
  • References (28)
    28 references, page 1 of 3

    [1] C. Auth, C. Allen, A. Blattner, et al., “A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors,” in Proc. Symp. VLSI Tech. Dig., 2012, pp.131-132.

    [2] N. Planes, O. Weber, V. Barral, et al., “28 nm FDSOI technology platform for high-speed low-voltage digital applications,” in Proc. Symp. VLSI Technol., Jun. 2012, pp. 133-134.

    [3] In E. Karl, Z. Guo, Y.-G. Ng, J. Keane, U. Bhattacharya, K. Zhang, “The impact of assist-circuit design for 22nm SRAM and beyond,” in Proc. IEEE IEDM, 2012, pp.561-564.

    [4] B. Nikolic, J.-H. Park, J. Kwak, et al., “Technology variability from a design perspective,” IEEE Trans. Circuits and systems-I: regular papers, vol.58 no.9, pp.1996-2009, Sept. 2011.

    [5] A. Asenov, “Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 µm MOSFETs: A 3D “atomistic” simulation study,” IEEE Trans. Electron Dev. Vol. 45, No. 12, pp. 2505-2513, 1998.

    [6] H. F. Dadgour, K. Endo, V. K. De, K. Banerjee, “Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors-Part I: Modeling, Analysis, and Experimental Validation,” IEEE Trans. Elec. Dev., vol.57 no.10, pp.2504-2514, Oct. 2010.

    [7] X. Wang, A. R. Brown, N. M. Idris, S. Markov, G. Roy and A. Asenov, “Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study,” IEEE Trans. on Electron Devices, Vol. 58, No. 8, pp. 2293-2301, Aug. 2011.

    [8] T. Matsukawa, Y. Liu, W. Mizubayashi, et al., “Suppressing Vt and Gm variability of FinFETs using amorphous metal gates for 14nm and beyond,” in Proc. IEDM, 2012, pp.8.2.1-8.2.4

    [9] A. Asenov, S. Kaya and A. R. Brown, “Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness,” IEEE Trans. on Electron Devices, Vol. 50, No. 5, pp. 1254-1260, 2003.

    [10] X. Wang, B. Cheng, A. R. Brown, C. Millar, J. B. Kuang, S. Nassif, and A. Asenov, “Interplay between process-induced and statistical variability in 14-nm CMOS technology double-gate SOI FinFETs,” IEEE Trans. on Electron Devices, Vol.60 No.8, pp.2485-2492, August 2013.

  • Similar Research Results (1)
  • Metrics
    No metrics available
Share - Bookmark