Synthesis of reconfigurable multiplier blocks: part II: algorithm

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Demirsoy, Suleyman S. ; Kale, Izzet ; Dempster, Andrew G.

Reconfigurable Multiplier Blocks (ReMB) offer significant area, delay and possibly power reduction in time-multiplexed\ud implementation of multiple constant multiplications. This paper and its companion paper (entitled Part I- Fundamentals) together present a systematic synthesis\ud method for Single Input Single Output (SISO) and Single\ud Input Multiple Output (SIMO) ReMB designs. This paper\ud illustrates the synthesis method through examples. The\ud companion paper presents the necessary foundation and\ud terminology needed for developing a systematic synthesis\ud technique. The proposed method achieves reduced logic-depth\ud and area over standard multipliers / multiplier blocks.
  • References (4)

    [1] Demirsoy S. S., I. Kale, A. G. Dempster, “Synthesis of reconfigurable multiplier blocks:Part I-Fundamentals”, to be published IEEE ISCAS'05.

    [2] Demirsoy S. S., “Complexity Reduction in Digital Filters and Filter Banks”, Ph.D. Thesis, University of Westminster, October 2003

    [3] Demirsoy S. S., A.G. Dempster and I. Kale, “Efficient Implementation of Digital Filters using Reconfigurable Multiplier Blocks”, .Asilomar Conf. on Signal, Systems and Computers,November 2004, CA

    [4] Dempster A.G. and Macleod M.D., “Use of minimum-adder multiplier-blocks in FIR digital filters”, IEEE Trans. CAS-II, vol. 42, no. 9, pp. 569-577, November 1995.

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