Performance analysis of general purpose and digital signal processor kernels for heterogeneous systems-on-chip
Other literature type
Noll, T. G.
(issn: 1684-9973, eissn: 1684-9973)
Various reasons like technology progress, flexibility
demands, shortened product cycle time and shortened
time to market have brought up the possibility and necessity
to integrate different architecture blocks on one heterogeneous
System-on-Chip (SoC). Architecture blocks like programmable
processor cores (DSP- and GPP-kernels), embedded
FPGAs as well as dedicated macros will be integral parts
of such a SoC. Especially programmable architecture blocks
and associated optimization techniques are discussed in this
contribution. Design space exploration and thus the choice
which architecture blocks should be integrated in a SoC is
a challenging task. Crucial to this exploration is the evaluation
of the application domain characteristics and the costs
caused by individual architecture blocks integrated on a SoC.
An ATE-cost function has been applied to examine the performance
of the aforementioned programmable architecture
blocks. Therefore, representative discrete devices have been
analyzed. Furthermore, several architecture dependent optimization
steps and their effects on the cost ratios are presented.