Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints

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D. Ludovici; F. Gilabert; S. Medardoni; C. Gómez; M. Gómez; P. López; G. Gaydadjiev; D. Bertozzi;

Most of past evaluations of fat-trees for on-chip interconnection networks rely on oversimplifying or even irrealistic architecture and traffic pattern assumptions, and very few layout analyses are available to relieve practical feasibility concerns in nanoscale technol... View more
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