publication . Article . Book . Part of book or chapter of book . Other literature type . Conference object . 2010

Networks-On-Chip

from research to products

Benini, Luca; De Micheli, Giovanni; Bertozzi, Davide; Cidon, Israel; Goossens, Kees; Kim, Kwanho; Lee, Kangmin; Lee, Se Joong; Murali, Srinivasan; Yoo, Hoi Jun;

Closed Access

Published: 13 Jun 2010

Summary

Abstract

This chapter presents the main technological challenges of networks-on-chip (NoC) architectures and a circuit analysis of NoC architectures using very large scale integration models, taking into account the interaction of network structure and implementation technology. NoC constitute an emerging technology for systems on chip (SoC), which can benefit significantly from the techniques of network systems architecture, more specifically from switching architectures. Architectural and circuit design methods are critical in the design and evaluation of NoC architectures, considering the strong dependency of NoC on implementation technology and the requirements of No...

doi: 10.1145/1837274.1837352 , 10.1007/978-1-4020-6488-3_8 , 10.1016/b978-0-12-373892-9.00012-8 ,

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Subjects

ACM Computing Classification System: Hardware_INTEGRATEDCIRCUITSHardware_PERFORMANCEANDRELIABILITY

free text keywords: Rendering (computer graphics), IBM, Embedded system, business.industry, business, Computation, Computer science, Software portability, Very-large-scale integration, Integrated circuit, law.invention, law, Traffic generation model, Multiprocessing, Routing algorithm, Flow control (data), Engineering, Computer architecture, Communication design, Interconnection, Quality of service, Systems architecture, Network analysis, Emerging technologies, Network architecture, Network structure, Network topology, Circuit design, Power consumption, Network on a chip, Electronic engineering, System on a chip, Timing closure, Integrated circuit design, Real-time computing, Fat tree, Architecture, Electronics, Polygon mesh, Computer Science(all)

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