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Other research product . Other ORP type . 2014

Alignment of Memory Transfers of a Time-Predictable Stack Cache

Abbaspour, Sahar; Brandner, Florian;
English
Published: 08 Oct 2014
Publisher: HAL CCSD
Country: France
Abstract

N/A; Modern computer architectures use features which often com-plicate the WCET analysis of real-time software. Alterna-tive time-predictable designs, and in particular caches, thus are gaining more and more interest. A recently proposed stack cache, for instance, avoids the need for the analysis of complex cache states. Instead, only the occupancy level of the cache has to be determined. The memory transfers generated by the standard stack cache are not generally aligned. These unaligned accesses risk to introduce complexity to the otherwise simple WCET analysis. In this work, we investigate three different ap-proaches to handle the alignment problem in the stack cache: (1) unaligned transfers, (2) alignment through compiler-gen-erated padding, (3) a novel hardware extension ensuring the alignment of all transfers. Simulation results show that our hardware extension offers a good compromise between average-case performance and analysis complexity.

Subjects

Block-Aligned Stack Cache, Alignment, Real-Time Systems, [INFO.INFO-PL]Computer Science [cs]/Programming Languages [cs.PL], [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF], [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Related Organizations
13 references, page 1 of 2

[1] S. Abbaspour, F. Brandner, and M. Schoeberl. A time-predictable stack cache. In Proc. of the Workshop on Software Technologies for Embedded and Ubiquitous Systems. 2013. [OpenAIRE]

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[5] A. Jordan, F. Brandner, and M. Schoeberl. Static analysis of worst-case stack cache behavior. In Proc. of the Conf. on Real-Time Networks and Systems, pages 55-64. ACM, 2013.

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[7] S. Park, H. woo Park, and S. Ha. A novel technique to use scratch-pad memory for stack management. In In Proc. of the Design, Automation Test in Europe Conference, DATE '07, pages 1-6. ACM, 2007.

[8] J. Reineke, I. Liu, H. D. Patel, S. Kim, and E. A. Lee. PRET DRAM controller: Bank privatization for predictability and temporal isolation. In Proc. of the Conference on Hardware/Software Codesign and System Synthesis, pages 99-108. ACM, 2011.

[9] S.Abbaspour, A. Jordan, and F. Brandner. Lazy spilling for a time-predictable stack cache: Implementation and analysis. In Proc. of the International Workshop on Worst-Case Execution Time Analysis, volume 39 of OASICS, pages 83-92. Schloss Dagstuhl, 2014. [OpenAIRE]

[10] M. Schoeberl, P. Schleuniger, W. Puffitsch, F. Brandner, C. Probst, S. Karlsson, and T. Thorn. Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach, volume 18, pages 11-21. OASICS, 2011. [OpenAIRE]

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Funded by
EC| T-CREST
Project
T-CREST
Time-predictable Multi-Core Architecture for Embedded Systems
  • Funder: European Commission (EC)
  • Project Code: 288008
  • Funding stream: FP7 | SP1 | ICT
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