Moore’s law has enabled the $4 trillion worldwide IT industry to nearly double the performance and functionality of digital electronics roughly every two years within a fixed cost and area. However, the International Semiconductor Technology Blueprint (ITRS) predicts that the technological underpinnings for Moore’s law will end by 2025. IRTS points out that two-dimensional (2D) materials will bring new opportunities for the Post-Moore Era, especially for the CMOS technology beyond 5 nm node. However, very few 2D materials based electronic products are available commercially over the decades of study. With the scaling-down of the electronic devices, it is urgent for academia and industry to seek ways to integrate 2D materials in practical and commercial electronic devices. Introducing 2D materials in the structure of commercial electronic devices is challenging due to their complex synthesis and manipulation. The 2D-HETERO project will explore large wafer-scale (from 2-inch to 300 mm) and uniform growth of different 2D materials by chemical vapor deposition (CVD) method. Van der Waals heterostructures based on different 2D materials will be developed by stacking 2D materials through the direct growth or through clean and large wafer-scale transfer methods. The developed high quality and wafer-scale van der Waals heterostructures will be integrated in different nanoelectronics (mainly field effect transistors), with the goal of enhancing the device performance, yield and uniformity. Using an interdisciplinary approach that combines materials science, physics, electrical engineering, industry-relevant nanofabrication and characterization, 2D-HETERO will pave the way to industrialize 2D materials based nanoelectronics. The combination of learning through research and a comprehensive training plan, including both scientific and technological as well as soft skills, will strongly enhance the profile of the applicant and provide a boost for her future scientific career.

Fluorescent microscopy is an indispensable tool in biology and medicine that has fueled many breakthroughs in a wide set of sub-domains. Recently the world of microscopy has witnessed a true revolution in terms of increased resolution of fluorescent imaging techniques. To break the intrinsic diffraction limit of the conventional microscope, several advanced super-resolution techniques were developed, some of which have even been awarded with the Nobel Prize in 2014. High resolution microscopy is also responsible for the spectacular cost reduction of DNA sequencing during the last decade. Yet, these techniques remain largely locked-up in specialized laboratories as they require bulky, expensive instrumentation and highly skilled operators. The next big push in microscopy with a large societal impact will come from extremely compact and robust optical systems that will make high-resolution (fluorescence) microscopy highly accessible, enabling both cellular diagnostics at the point of care and the development of compact, cost-effective DNA sequencing instruments, facilitating early diagnosis of cancer and other genomic disorders. IROCSIM will facilitate this next breakthrough by introducing a novel high-resolution imaging platform based entirely on an intimate marriage of active on-chip photonics and CMOS image sensors. This concept will completely eliminate the necessity of standard free-space optical components by integrating specially designed structured optical illumination, illumination modulation, an excitation filter and an image sensor in a single chip. The resulting platform will enable high resolution, fast, robust, zero-maintenance, and inexpensive microscopy with applications reaching from cellomics to DNA sequencing, proteomics, and highly parallelized optical biosensors.

The field of computing saw a breakthrough when quantum supremacy was established, and it was demonstrated that a classical computer will take 10,000 years for a task that a quantum processor based on superconducting qubits took 200 seconds. The future generation of computing hardware that can deliver high performance parallel computing include (i) High performance superconducting circuits-based computing hardware and (ii) quantum processors based on superconducting qubits. Key components of these technologies, like Superconducting Nanowire for Single-Photon Detectors (SNSPDs), cryogenic interconnects and ground plane electronics, use SUperconducting Nitrides (SUNs) such as NbN, TiN and NbTiN. However, despite the heavy reliance on SUNs, optimal deposition processes to engineer these materials to meet the challenges of the technology are still lacking. The desirable process should be able to engineer the features of conformality, provide continuous, pin-hole free films with controlled thicknesses between 2-5 nm, occur at low temperatures and in some applications provide selectivity to reduce the patterning overhead. This project addresses this gap in SUN material engineering by generating scientific understanding that is pivotal to enabling the quantum processors in the future. We intend to do so by investigating novel chemistries and sequences of Atomic Layer Deposition (ALD) coupled with surface functionalization in order to enable the fabrication of CMOS industry compatible, area Selective ALD at Low Temperature (SALT) of the widely used SUNs of NbN, TiN and NbTiN. This project will increase the understanding of ALD using reducing agents and inhibitors, advance the science of area selective ALD and enable higher fidelity qubits. Therefore, this research contributes to advancing chemical science and caters to the critical needs of the superconducting digital electronics as well as quantum processor hardware since SUNs are ubiquitous to both technologies.

Interconnects impose major limits on the performance on integrated circuits during the exponential reduction of feature size of microchips. The semiconductor industry faces challenges in the metallization of interconnects below the 10 nm half pitch and is looking to alternative metallization schemes to replace copper, the traditional choice for the last 20 years, which no longer meet the conductivity requirements at decreasing length scales. Binary metals such as nickel-aluminium (NiAl) have been identified as a promising candidate that performs well with respect to resistivity at critical dimensions (sub-10 nm) to replace copper. However, there are several challenges associated with the instability of these materials regarding surface oxidation, leading to performance degradation. The objective of CRIME is the in-situ removal of the surface oxide and in-situ passivation of binary intermetallic compounds to prevent surface oxidation at the sub-10 nm half pitch for interconnect applications. To meet the future size requirements of interconnects, the downscaling of the cleaning and passivation processes from blankets to sub-10 nm half-pitch and the formation of patterned lines, with the aim of sub-7 nm half-pitch, will be performed. This will be achieved through an interdisciplinary approach that combines material science, chemistry, chemical engineering, nanoelectronics, and physics, to test different metal oxide removal and surface cleaning chemistries in combination with organic and inorganic passivation layers in-situ to overcome the formation of an oxide top layer. The passivation layers will be deposited in the liquid and vapour phase and various analytic techniques will be used to elucidate the surface chemistry and surface reaction mechanisms. CRIME goes beyond the state-of-the-art as the cleaning and passivating process and the downscaling of these processes on NiAl at the nanoscale and for advanced microelectronics nodes has not been previously demonstrated

This proposal presents an interdisciplinary, forward looking, training-by-research plan in the field of physical reliability modeling of emerging transistors and materials beyond 2020. Its main goal is development and validation of a simulation framework which self-consistently considers the main reliability phenomena including bias temperature instability, hot-carrier degradation, and self-heating. These effects were suggested to be the response of interface and oxide defects/precursors which can be activated by different driving forces determined by device operating conditions and specifics of the device topology. Thus, the core of this project will be put on a detailed microscopic description of the properties of defects/precursors, which will be studied experimentally and theoretically. Within this defect-centric paradigm we will address reliability issues in devices with emerging architectures, i.e. fin and nanowire transistors, high-k gate dielectrics, and high mobility channel materials such as SiGe, Ge, and III-V alloys. The unifying model building on the microscopic defect properties will be validated over a wide range of device bias conditions. We will capture the parasitic effect of self-heating which has a strong impact on the energetic distribution of hot carriers and hence on hot-carrier degradation. Special attention will be paid to time-dependent variability of device characteristics which is a response of nanoscale devices on activation/deactivation of individual defects. Knowledge acquired within this project will be valuable for applied and fundamental physics, material science, computational chemistry, electrical engineering, VLSI technology, and circuit design. The research and training activities will enhance applicant’s future career by broadening his professional skills and expertise, expose him to industrial requirements, and open new perspectives for future collaboration with industry.