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5 research outcomes, page 1 of 1
  • publication . Article . Preprint . 2012
    Open Access English
    Authors:
    Tobias Flick; Yunpeng Lu; Alex Sood; Daniel Dobos; Daniel Dzahini; Edwin Spencer; Michal Sloboda; Patrick Skubic; Oswin Ehrmann; Yoshinobu Unno; ...
    Publisher: HAL CCSD
    Project: NSERC , EC | AIDA (262025)

    Comment: 45 pages, 30 figures, submitted to JINST

  • publication . Article . Conference object . 2011
    Open Access English
    Authors:
    R. Kluit; Giovanni Darbo; Malte Backhaus; Mohsine Menouni; Marlon Barbero; L. Gonella; Alexandre Rozanov; J. Fleury; Frank Jensen; J.D. Schipper; ...
    Publisher: JINST
    Project: EC | AIDA (262025)

    International audience; The FE-I4 is a new pixel readout integrated circuit designed to meet the requirements of ATLAS experiment upgrades. The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the requested performances....

  • publication . Article . Conference object . 2013
    Open Access English
    Authors:
    Theresa Obermann; D. Arutinov; F. Bompard; S Rozanov; P. Breugnon; Tomasz Hemperek; S. Godiot; Hans Krüger; Marlon Barbero; Norbert Wermes; ...
    Publisher: JINST
    Project: EC | AIDA (262025)

    International audience; To face new challenges brought by the upgrades of the LargeHadron Collider at CERN and of the ATLAS pixels detector, for whichhigh spatial resolution, very good signal to noise ratio and highradiation hardness is needed, 3D integrated technologie...

  • publication . Article . Conference object . Other literature type . 2012
    Open Access
    Authors:
    M. A. Kagan;
    Publisher: Elsevier BV
    Project: EC | AIDA (262025)

    \nPDF\nOverview of the ATLAS Insertable B-Layer (IBL) Project\nSubmitted by Clara Troncon on 30 May 2013 at 23:12\nId: 5\nLast modification: 30 May 2013 23:12\nContribution type: ORAL\nContent\nThe upgrades for the ATLAS Pixel Detector will be staged in preparation for ...

  • publication . Conference object . Article . 2012
    Open Access English
    Authors:
    Maurice Garcia-Sciveres; F. Gensolen; P. Breugnon; Y. Lu; Malte Backhaus; J.D. Schipper; R. Kluit; L. M. Caminada; D. Arutinov; A. Mekkaoui; ...
    Publisher: HAL CCSD
    Project: EC | AIDA (262025)

    International audience; The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DIC...

5 research outcomes, page 1 of 1